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mmCPF_UTCL1_CNTL
sys/dev/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2316
#define mmCPF_UTCL1_CNTL 0x103e
sys/dev/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
2630
#define mmCPF_UTCL1_CNTL 0x103e
sys/dev/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
2568
#define mmCPF_UTCL1_CNTL 0x103e
