Symbol: UVD_CGC_CTRL__MPC_MODE_MASK
sys/dev/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
48
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
sys/dev/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
255
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
sys/dev/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
277
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
sys/dev/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
279
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
sys/dev/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
458
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
sys/dev/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
946
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L