sys/dev/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h

307

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018

sys/dev/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h

3758

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

5192

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

5384

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

4372

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

5492

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

5396

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18

sys/dev/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h

1994

#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18